1. Field of the Invention
The embodiments of the invention generally relate to integrated circuit technology, and, more particularly, to methods to form a customized field effect transistor (FET).
2. Description of the Related Art
Motivation to form FinFET devices on very thin silicon rail as the body of a metal oxide semiconductor field effect transistor (MOSFET) is driven by the need for shorter gate lengths, lower leakage currents, and a higher level of device integration. The lack of a reliable high-k gate stack to limit the leakage current makes the three-dimensional structure of thin body, known as a “fin” in U.S. Pat. No. 6,252,284, the complete disclosure of which is herein incorporated by reference, very attractive in 90-nanometer process node and beyond. The fin body is normally gated on three sides to gain better control of the channel potential, thus resulting in better short channel effect and scalability. Methods for forming such FinFET devices face significant challenges such as sub-lithographic dimension control of the fin width in a manufacturing environment, and surface planarity to facilitate back-end-of-line metallization. Although the fin dimensions in the conventional devices may be defined by any conventional lithographic methods, it is desirable to further reduce the fin dimension to less than 30 nm, which is beyond the capability of existing lithographic technology.